DDR Phy

Krivi provides state-of-art memory interface (DDR) PHY, IO pad libraries and Analog clocking IPs. Our deep domain expertise, silicon proven technology and design automation enables us to deliver customized high performance DDR PHYs resulting in best PPA in industry. Krivi’s DDR3/LPDDR3,2 combo PHY achieves 2.13Gbps speed in 4 layer plastic BGA wire-bond package. Krivi PHY technology allows implementing 3.2Gbps DDR4/LPDDR4 in 28nm process node.

We are preferred partner for some of the world top-20 semiconductor companies for customized IO pad libraries targeting low leakage, high voltage, multi-standard, multi-function or higher ESD levels over foundry provided libraries. Our silicon validated Alcor platform provides IO pad library for wide range of standards including DDR4/3, LPDDR3/2, HSTL, RLDRAM-3, LVDS, subLVDS, SLVS, UHS-II, SDIO, MMC, eMMC and high voltage IO in 28nm. This IO library platform is easily portable across most of the popular technology nodes using in-house library generation and qualification software.

Krivi’s ASIC PLL comes with programmable option for spread-spectrum and fractional clocking. Krivi is working with one of the leading foundries to provide battery powered ultra-low power RTC clock IP targeting IOT applications.

At Krivi we understand importance of working IP for your SoC and investment. We have developed comprehensive testchip and pre-silicon verification infrastructure and to ensure first time silicon success. Being a small company, we also offer customization and support that helps to differentiate your SoC from competition. Meet us to discuss how we can provide best Performance, Power and Area in our IPs that helps you succeed.