CPU Peripherals

AndeShape™ Platform IP

AE210P – Generic Platform IP for Micro-Controllers

General Description

AE210P is a generic SoC platform IP which provides users with high flexibility, low cost and fast time to market for micro-controller applications such as Internet of Things (IoT) and Wearable Computing. To minimize the cost, the bus structure of AE210P can be simplified to one APB only. To maximize the performance, AE210P can be configured to add an AHB bus matrix. All the bus controllers, bridges, and peripheral IPs of AE210P are designed to minimize the access latency, the logic gate count, and the power consumption. Through the provided interfaces, users’ designs can be easily integrated to the platform.

Block Diagram

AE210P with APB bus only

pip_1

AE210P with AHB Bus Matrix

pip_2

Feature Highlight

Bus Controller / Bridge

  • AHB Bus Matrix Controller (BMC)
  • AHB-to-APB Bridge (APBBRG)
  • APB Decoder (APBDEC)

AHB Bus Components

  • DMA Controller (DMAC)
  • Local Memory Bridge (LMBRG)

APB Bus Components

  • UART Controller
  • SPI Controller
  • I2C Controller (IIC)
  • GPIO
  • Timer (PIT) / PWM
  • Watchdog Timer (WDT)
  • Real Time Clock (RTC)

Architecture

  • Supports AndesCore™ N7/N8/N9/N10
  • Provides two bus structures
    • APB-only
    • AHB bus matrix with APB
  • Provides interfaces for design extension/integration
    • AHB master/slave interfaces
    • APB slave interface
    • Interrupt signals
    • DMA handshake signals

AG101P – Generic Platform IP for Embedded Systems

General Description

AG101P is a generic SoC Platform IP that works with any of AndesCore™ processors to provide a cost-effective and high performance solution for majority of embedded systems in variety of application domains. Users may simply attach their IP on one of the system buses together with certain glue logics to complete a SoC solution for a specific application. With comprehensive simulation and design environments, users may evaluate the system performance of their applications and track bugs of their designs efficiently. The optional hardware development platform further provides real system environment for early prototyping and software/hardware co-development.

Block Diagram

pip_3

Feature Highlight

Architecture

  • AMBA AHB bus for high speed devices
  • AMBA APB bus for low speed devices
  • Dedicated DRAM interface for DMA and LCD controller
  • Support AndesCore™ processor(s)

AHB Bus Components

  • AHB bus controller
  • SDRAM controller
  • Static memory controller
  • Ethernet MAC 10/100
  • DMA controller
  • LCD controller
  • AHB-to-APB bridge

APB Bus Components

  • Timer
  • Watch Dog Timer
  • Real Time Clock
  • Interrupt controller
  • GPIO
  • Pulse Width Modulator
  • I²C controller
  • Serial controller for SSP/SPI/I2S/AC97
  • SD/MMC host controller
  • Timer
  • UART controller

External Memory Interface

  • SDRAM/SRAM/ROM/Flash